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Digital Design Entry Methods

posted Aug 13, 2018, 9:51 PM by MUHAMMAD MUN`IM AHMAD ZABIDI   [ updated Sep 19, 2018, 9:59 PM ]

  • Schematic capture: for small designs
  • Hardware description language (HDL) such as Verilog and VHDL: medium to large designs
  • High-level synthesis (HLS) such as Vivado-HLS. Design is entered using C, and converted to HDL.
  • OpenCL: framework for writing parallel programs for CPU, GPU & FPGA. Based on C99 and C++11.
The most popular system-level development tools are Vivao HLS and Altera SDK for OpenCL. Vivado HLS requires more hardware knowledge. Altera OpenCL is relatively easier for software programmers but uses more FPGA resources.


Qin, S., & Berekovic, M. (2015). A Comparison of High-Level Design Tools for SoC-FPGA on Disparity Map Calculation Example. In 2nd International Workshop on FPGAs for Software Programmers (FSP 2015). Retrieved from