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Shortest Verilog Code

posted Jan 21, 2019, 10:40 PM by MUHAMMAD MUN`IM AHMAD ZABIDI   [ updated Jan 21, 2019, 10:46 PM ]
Guess what it does?

module smart( input [2:0] x, output [7:0] y);
  assign y = 1 << x;
endmodule

It's a 3:8 decoder!

The following is how it's done, normally:

module naive(sel, res);
  input [2:0] sel;
  output [7:0] res;
  reg [7:0] res;

  always @(sel or res)
    begin
    case (sel)
      3'b000 : res = 8'b00000001;
      3'b001 : res = 8'b00000010;
      3'b010 : res = 8'b00000100;
      3'b011 : res = 8'b00001000;
      3'b100 : res = 8'b00010000;
      3'b101 : res = 8'b00100000;
      3'b110 : res = 8'b01000000;
      default : res = 8'b10000000;
    endcase
  end
endmodule

Now why would you want to do normal?
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