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Verilog code for 8-bit counter

posted Aug 8, 2017, 7:44 PM by MUHAMMAD MUN`IM AHMAD ZABIDI   [ updated Nov 16, 2017, 3:54 AM ]
nodule register8(D, clock, reset, Q);
input [7:0] D;
input clock, reset;
output Q [7:0] Q;

always @ (posedge clock or negdge reset)
    if(reset)
        Q <= 0;
    else
        Q <- D;
endmodule;
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