Programmable CPLD Timer

Post date: Jan 30, 2018 4:13:53 PM

We describe a programmble timer which produces a pulse with a length determined by the binary value at input x.

The circuit contains a 1 Hz timing generator, a counter, a comparator and an SR latch.

A 50 MHz system clock is assumed.

The Trig signal initiates timer operation. It is connected to 3 points in the module. At the timing reference, Trig loads 50 million into the 26-bit accumulator. At the counter, Trig clears the counter to 0. At the output SR latch, Trig sets Out to high.

The timing reference produces a pulse one clock cycle wide every second. The pulse, labeled Z, enables the counter so that the counter increases by 1 every second.

The comparator outputs a reset pulse to the SR latch when counter value equals X.

If you just want a 1 second pulse, connect Z to the set input of the latch (and skip the counter and comparator).